Data block manipulation for error rate reduction in STT-MRAM based main memory
Author:
Publisher
Springer Science and Business Media LLC
Subject
Hardware and Architecture,Information Systems,Theoretical Computer Science,Software
Link
https://link.springer.com/content/pdf/10.1007/s11227-022-04394-7.pdf
Reference61 articles.
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2. Lee B, Ipek E, Mutlu O, Burger D (2009) Architecting phase change memory as a scalable dram alternative. ACM SIGARCH Comput Archit News 37(3):2–13. https://doi.org/10.1145/1555754.1555758
3. Komalan M, Rock O. H, Hartmann M, Sakhare S, Tenllado C (2018) Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks. In: Proceedings of the Conference on Design, Automation and Test in Europe (DATE), pp 103–108. Doi: https://doi.org/10.23919/DATE.2018.8341987
4. Khajekarimi E, Jamshidi K, Vafaei A (2019) Energy minimization in the STT-RAM-based high-capacity last-level caches. J Supercomput 75(10):6831–6854. https://doi.org/10.1007/s11227-019-02918-2
5. Guo X, Bojnordi MN, Guo Q, Ipek E (2017) Sanitizer: mitigating the impact of expensive ecc checks on stt-mram based main memories. IEEE Trans Comput 67(6):847–860. https://doi.org/10.1109/TC.2017.2779151
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