Optimization of ISBD embedded SiGe layers to prevent delamination process for MOSFET applications

Author:

Wasyluk Joanna,Ge Yang,Wurster Kai,Lenski Markus,Reichel Carsten

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference7 articles.

1. Ghani T, Armstrong M, Auth C, et al. A 90-nm high volume manufacturing logic technology featuring novel 45-nm gate length strained silicon CMOS transistors. In: IEDM Tech Dig; 2003. p. 978–80.

2. Nouri F, Verheyen P, et al. A systematic study of trade-offs in engineering a locally strained pMOSFET. In: IEDM Tech Dig, vol. 107; 2004. p. 1055–8.

3. Growth kinetics and B-doping of very high G content Si1−xGex for source and drain engineering;Hartmann;ECS Trans,2007

4. A smarter-cut approach to low temperature silicon layer transfer;Tong;Appl Phys Lett,1998

5. The influence of boron ion implantation on hydrogen blister formation in n-type silicon;Höchbauer;J Appl Phys,1999

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