Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession-Reference-Cited by-同舟云学术

Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession

Published:2010-09 Issue:9 Volume:54 Page:855-860
ISSN:0038-1101
Container-title:Solid-State Electronics
language:en
Short-container-title:Solid-State Electronics

Author:

Chiarella T.,Witters L.,Mercha A.,Kerner C.,Rakowski M.,Ortolland C.,Ragnarsson L.-Å.,Parvais B.,De Keersgieter A.,Kubicek S.,Redolfi A.,Vrancken C.,Brus S.,Lauwers A.,Absil P.,Biesemans S.,Hoffmann T.

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference17 articles.

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2. van Dal MJH, Collaert N, Doornbos G, Vellianitis G, Curatola G, Pawlak BJ et al. Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography. VLSI; 2007. p. 110–1.

3. Veloso A, van Dal MJH, Collaert N, De Keersgieter A, Witters L, Rooyackers R et al. Characteristics and integration challenges of FinFET-based devices for (sub-) 22nm technology nodes circuit applications. SSDM; 2009. p. 1040–1.

4. The International Technology Roadmap for Semiconductors (ITRS); 2008. .

5. Veloso A, Witters L, Demand M, Ferain I, Son NJ, Kaczer B et al. Flexible and robust capping-metal gate integration technology enabling multiple-VT CMOS in MuGFETs. VLSI; 2008. p. 14–5.

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