Design and optimization of high voltage LDMOS transistors on 0.18μm SOI CMOS technology-Reference-Cited by-同舟云学术

Design and optimization of high voltage LDMOS transistors on 0.18μm SOI CMOS technology

Published:2011-07 Issue:1 Volume:61 Page:111-115
ISSN:0038-1101
Container-title:Solid-State Electronics
language:en
Short-container-title:Solid-State Electronics

Author:

Toulon G.,Cortés I.,Morancho F.,Hugonnard-Bruyère E.,Villard B.,Toren W.J.

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference13 articles.

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3. Zhu R, Khemka V, Bose A, Roggenbauer T. Stepped-drift LDMOSFET: a novel drift region engineering device for advanced smart power technologies. In: Proc ISPSD; 2006. p. 1–4.

4. Static and dynamic electrical performances of STI thin-SOI power LDMOS transistors;Cortés;Semicond Sci Technol,2008

5. A 700V Interface IC for power bridge circuits;Schoofs;IEEE J Solid-state circ,1990

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