Simulation Study on the Optimization and Scaling Behavior of LDMOS Transistors for Low-Voltage Power Applications
Author:
Funder
Texas Instruments Inc
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/9237191/09187583.pdf?arnumber=9187583
Cited by 15 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Carrier transport simulation methods for electronic devices with coexistence of quantum transport and diffusive transport;Journal of Applied Physics;2024-06-11
2. Applicability of Channel Doping Gradient in the Design of a Short Channel (0.1 µm) LDMOS Transistor for Integrated Power and RF Applications;Transactions on Electrical and Electronic Materials;2024-04-04
3. Performance enhancement of 1.7 kV MOSFET using PIN-junction gate and integrated heterojunction;Microelectronics Reliability;2024-01
4. Experiments of a Novel Low-Voltage LDMOS With Ultrashallow Low-Resistance Path Modulated by Bulk Superjunction;IEEE Transactions on Electron Devices;2024-01
5. A Physics-Based Compact Model for the Static Drain Current in Heterojunction Barrier CNTFETs—Part II: Scattering, High-Field Effects, and Model Verification;IEEE Transactions on Electron Devices;2024-01
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