Author:
Choi Woo Young,Choi Byung Yong,Kim Dong-Won,Lee Choong-Ho,Park Donggun,Lee Jong Duk,Park Byung-Gook
Subject
Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Reference7 articles.
1. Device scaling limits of Si MOSFETs and their application dependencies;Frank;Proc IEEE,2001
2. Scalable 2-bit silicon–oxide–nitride–oxide–silicon (SONOS) memory with physically separated local nitrides under a merged gate;Lee;Solid-State Electron,2004
3. Variable supply-voltage scheme for low-power high-speed CMOS digital design;Kuroda;IEEE J Solid-State Circ,1998
4. Choi BY, Park B-G, Lee YK, Sung SK, Kim TY, Cho ES, et al. Highly scalable and reliable 2-bit/cell SONOS memory transistor beyond 50nm NVM technology using outer sidewall spacer scheme with damascene gate process. Symposium on VLSI Technology 2005. p. 118–9.
5. Investigation of lateral charge distribution of 2-bit SONOS memory devices using physically separated twin SONOS structure;Choi;ICMTS,2006
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献