New program inhibition scheme for high boosting efficiency in three-dimensional NAND array
Author:
Publisher
IOP Publishing
Subject
General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering
Link
http://stacks.iop.org/1347-4065/53/i=7/a=070304/pdf
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1. Floating-Gate Coupling Canceller for Multi-Level Cell NAND Flash
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3. Extreme Short-Channel Effect on RTS and Inverse Scaling Behavior: Source–Drain Implantation Effect in 25-nm nand Flash Memory
4. 25-nm programmable virtual source/drain MOSFETs using a twin SONOS memory structure
5. Effects of floating-gate interference on NAND flash memory cell operation
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1. A Review of Cell Operation Algorithm for 3D NAND Flash Memory;Applied Sciences;2022-10-22
2. A Novel Program Scheme for Program Disturbance Optimization in 3-D NAND Flash Memory;IEEE Electron Device Letters;2018-07
3. Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices;Computers;2017-04-21
4. Disturbance Relaxation for 3D Flash Memory;IEEE Transactions on Computers;2016-05-01
5. Gated twin-bit silicon–oxide–nitride–oxide–silicon NAND flash memory for high-density nonvolatile memory;Japanese Journal of Applied Physics;2015-05-26
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