Performance analysis of parallel array of nanowires and a nanosheet in SG, DG and GAA FETs

Author:

Darbandy Ghader,Mothes Sven,Schröter Michael,Kloes Alexander,Claus Martin

Funder

German National Science Foundation

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference31 articles.

1. Density scaling beyond the FinFET: Architecture considerations for gate-all-around CMOS;Guillorn,2016

2. Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain;Barraud,2016

3. Three-dimensional transport simulations and modeling of densely packed CNTFETs;Mothes;IEEE Trans Nanotechnol,2018

4. Modeling and analysis of planar-gate electrostatic capacitance of 1-D FET with multiple cylindrical conducting channels;Deng;IEEE Trans Electron Devices,2007

5. Gate capacitance optimization for arrays of carbon nanotube field-effect transistors;Wang,2003

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