Influence of device architecture on junction leakage in low-temperature process FDSOI MOSFETs

Author:

Sklenard Benoit,Batude Perrine,Rafhay Quentin,Martin-Bragado Ignacio,Xu Cuiqin,Previtali Bernard,Colombeau Benjamin,Khaja Fareen-Adeni,Cristoloveanu Sorin,Rivallin Pierrette,Tavernier Clement,Poiroux Thierry

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference17 articles.

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3. Veloso A, Ragnarsson L-A, Cho M, Devriendt K, Kellens K, Sebaai F, et al. Gate-last vs. gate-first technology for aggressively scaled EOT logic/RF CMOS. In: 2011 Symposium on VLSI technology (VLSIT); 2011. p. 34–5.

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1. Multiscale modeling of doping processes in advanced semiconductor devices;Materials Science in Semiconductor Processing;2017-05

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