Substrate bias effects on drain-induced barrier lowering in short channel PMOS devices at 77 K-Reference-Cited by-同舟云学术

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Substrate bias effects on drain-induced barrier lowering in short channel PMOS devices at 77 K

Published:1990-12 Issue:12 Volume:30 Page:1160-1165
ISSN:0011-2275
Container-title:Cryogenics
language:en
Short-container-title:Cryogenics

Author:

Yan Z.X.,Deen M.J.

Publisher

Elsevier BV

Subject

General Physics and Astronomy,General Materials Science

Reference19 articles.

1. Cryogenic operation of CMOS-based microsystems and computers;Deen,1989

2. Low-temperature electronics;Kirschman;IEEE Circ Dev Mag,1990

3. Design considerations for the operation of CMOS inverters at cryogenic temperatures;Deen,1988

4. 1.5 μm gate CMOS operated at 77 K;Kato;IEDM Tech Dig,1984

5. Digital characteristics of CMOS devices at cryogenic temperatures;Deen;IEEE J Sol St Circ,1989

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Cryogenic Transport Characteristics of P-Type Gate-All-Around Silicon Nanowire MOSFETs;Nanomaterials;2021-01-26

2. In depth static and low-frequency noise characterization of n-channel FinFETs on SOI substrates at cryogenic temperature;Solid-State Electronics;2014-08

3. Low temperature operation of ultra-thin gate oxide sub-0.1 μm MOSFETs;Journal de Physique IV (Proceedings);2002-05

4. Suppression of hot-carrier-induced degradation in n-mosfets at low temperatures by N2O-nitridation of gate oxide;Solid-State Electronics;1998-04

5. Brief review of the MOS device physics for low temperature electronics;Solid-State Electronics;1994-12

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