Bus-driven floorplanning with bus pin assignment and deviation minimization-Reference-Cited by-同舟云学术

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Bus-driven floorplanning with bus pin assignment and deviation minimization

Published:2012-09 Issue:4 Volume:45 Page:405-426
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Wu Po-Hsun,Ho Tsung-Yi

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference16 articles.

1. Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs;Rafiq;Proceedings of ISPD,2002

2. Bus-driven floorplanning;Xiang;Proceedings of ICCAD,2003

3. Modern floorplanning based on fast simulated annealing;Chen;Proceedings of ISPD,2005

4. Multi-bend bus driven floorplanning;Law;Integration: The VLSI Journal,2008

5. OPC-friendly bus driven floorplanning;Xiang;Proceedings of ISQED,2007

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2019-06

2. Bus-driven floorplanning with thermal consideration;Integration;2013-09

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