Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Reference24 articles.
1. K. Sundaresan, N.R. Mahapatra, Accurate energy dissipation and thermal modeling for nanometer-scale buses, in: Proceedings of the IEEE International Symposium HPCA, East Lansing, MI, USA, February 2005, pp. 51–60.
2. F. Wang, Y. Xie, N. Vijaykrishnan, M.J. Irwin, On-chip bus thermal analysis and optimization, in: Proceedings of the IEEE/ACM DATE Conference, Munich, Germany, March 2006, pp. 1–6.
3. B. Wang, P. Mazumder, An accurate interconnect thermal model using equivalent transmission line circuit, in: Proceedings of the IEEE/ACM DATE Conference, Nice, France, April 2009, pp. 280–283.
4. F. Rafiq, M.C. Jeske, H.H. Yang, N. Sherwani, Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs, IEEE Transactions on CAD (June) (2003) 730–741.
5. H. Xiang, X. Tang, M.D.F. Wong, Bus-driven floorplanning, IEEE Transactions on CAD (November) (2004) 1522–1530.
Cited by
3 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献