A read-decoupled gated-ground SRAM architecture for low-power embedded memories

Author:

Hussain Wasim,Jahinuzzaman Shah M.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference15 articles.

1. Integrated MOS random-access memory;Schmidt;Solid-State Design,1965

2. An 8T-SRAM for variability tolerance and low-voltage operation in high-performance caches;Chang;IEEE Journal of Solid-State Circuits,2008

3. Characterization of a novel nine-transistor SRAM Cell;Liu;IEEE Transactions On Very Large Scale Integration (VLSI) Systems,2008

4. A transregional CMOS SRAM with single, logic VDD and dynamic power rails;Bhavnaganvala;Symposium On VLSl Circuits Digest of Technical Papers,2004

5. A 3-GHz 70-Mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply;Zhang;IEEE Journal of Solid-State Circuits,2006

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