A new leakage-tolerant domino circuit using voltage-comparison for wide fan-in gates in deep sub-micron technology-Reference-Cited by-同舟云学术

A new leakage-tolerant domino circuit using voltage-comparison for wide fan-in gates in deep sub-micron technology

Published:2015-09 Issue: Volume:51 Page:61-71
ISSN:0167-9260
Container-title:Integration, the VLSI Journal
language:en
Short-container-title:Integration, the VLSI Journal

Author:

Asyaei Mohammad^ORCID

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference49 articles.

1. CMOS: Circuit Design, Layout, and Simulation;Baker,2011

2. Domino logic designs for high-performance and leakage-tolerant applications;Moradi;Integr. VLSI J.,2013

3. J.-J. Kim, K. Roy, A leakage tolerant high fan-in dynamic circuit design technique, in: Proceedings of the 27th European Solid-State Circuits Conference, ESSCIRC, IEEE, 2001, pp. 309–312.

4. Low power wide gates for modern power efficient processors;Asyaei;Integr. VLSI J.,2014

5. Digital Integrated Circuits;Rabaey,2003

Cited by 43 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Circuit Techniques for High Performance in CDDK Domino Logic;2024 IEEE 4th International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA);2024-05-17

2. Evaluation of dual-ONOFIC method for subthreshold leakage reduction in domino circuit;International Journal of Electronics;2023-11-08

3. Analysis of High-Performance Near-threshold Dual Mode Logic Design;International Journal of Electronics and Telecommunications;2023-07-26

4. Reduction of variation and leakage in wide fan-in OR Logic domino gate;Integration;2023-03

5. A Novel Domino Logic Based on Floating-Gate MOS Transistors;Jordan Journal of Electrical Engineering;2023