Evaluation of dual-ONOFIC method for subthreshold leakage reduction in domino circuit-Reference-Cited by-同舟云学术

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Evaluation of dual-ONOFIC method for subthreshold leakage reduction in domino circuit

Published:2023-11-08 Issue: Volume: Page:1-17
ISSN:0020-7217
Container-title:International Journal of Electronics
language:en
Short-container-title:International Journal of Electronics

Author:

Magraiya Vijay Kumar¹,Gupta Tarun Kumar²,Verma Rajesh³,Pandey Amit Kumar⁴,Kori Shiv Prasad⁵

Affiliation:

1. Department of Electronics and Communication, MANIT, Bhopal, India

2. Department of Electronics and Communication, University of Allahabad, Prayagraj, India

3. Department of Electrical Engineering, King Khalid University, Abha, Kingdom of Saudi Arabia

4. Department of Applied Science and Humanities, Rajkiya Engineering College, Akbarpur, India

5. Department of Electronics and Communication, Jijamata, Government Polytechnic College, Burhanpur, India

Funder

no funding associated with the work

Publisher

Informa UK Limited

Subject

Electrical and Electronic Engineering

Link

https://www.tandfonline.com/doi/pdf/10.1080/00207217.2023.2278439

Reference25 articles.

1. A new leakage-tolerant domino circuit using voltage-comparison for wide fan-in gates in deep sub-micron technology

2. Cui, X., Ma, K., Liao, K., Liao, N., Wu, D., Wei, W., Li, R., & Yu, D. (2013). A dynamic-adjusting threshold-voltage scheme for FinFETs low power designs. IEEE International Symposium on Circuits and Systems (ISCAS2013), Beijing, China (pp. 129–132).

3. Ultra-low power FinFET-based domino circuits

4. Low power domino logic circuits in deep-submicron technology using CMOS

5. Lector with Footed-Diode Inverter: A Technique for Leakage Reduction in Domino Circuits

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