Dual-rail asynchronous logic multi-level implementation

Author:

Lemberski Igor,Fišer Petr

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference31 articles.

1. The first asynchronous microprocessor: the test results;Martin;ACM SIGARCH Computer Architecture News,1989

2. W.J. Bainbridge et al., Delay-Insensitive, Point-to-Point Interconnect using m-of-n codes, in: Proceedings of the 9th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'03), Vancouver, May 2003, pp. 132–140.

3. Asynchronous Sequential Switching Circuits;Unger,1969

4. S.M. Nowick, Automatic Synthesis of Burst-Mode Asynchronous Controllers, Ph.D. Thesis, Stanfort University, March 1993.

5. Exact two-level minimization of hazard-free logic with multiple-input changes;Nowick;IEEE Transactions on Computer-Aided Design,1995

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