A synchronous latency-insensitive RISC for better than worst-case design
Author:
Publisher
Elsevier BV
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Reference41 articles.
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1. Lifetime improvement by exploiting aggressive voltage scaling during runtime of error-resilient applications;Integration;2018-03
2. From Latency-Insensitive Design to Communication-Based System-Level Design;Proceedings of the IEEE;2015-11
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