Comments on “Dual-rail asynchronous logic multi-level implementation”
Author:
Publisher
Elsevier BV
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Reference37 articles.
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4. A.J. Martin, The limitation to delay-insensitivity in asynchronous circuits, in: Proceedings of the 6th MIT Conference on Advanced Research in VLSI, 1990, pp. 263–278.
5. Beware the isochronic fork;van Berkel;Integr. VLSI J.,1992
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