A statistics-based digital background calibration technique for pipelined ADCs
Author:
Publisher
Elsevier BV
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Reference20 articles.
1. A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification;Murmann;IEEE J. Solid-State Circuits,2003
2. Digital background correction of harmonic distortion in pipelined ADCs;Panigada;IEEE Trans. Circuits Syst. I: Regul. Pap.,2006
3. Background interstage gain calibration technique for pipelined ADCs;Keane;IEEE Trans. Circuits Syst. I: Regul. Pap.,2005
4. A 12-bit 200-MHz CMOS ADC;Sahoo;IEEE J. Solid-State Circuits,2009
5. Exploiting process variation and noise in comparators to calibrate interstage gain nonlinearity in pipelined ADCs;Sun;IEEE Trans. Circuits Syst. I: Regul. Pap,2012
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3. Digital Calibration of Elements Mismatch in Multirate Predictive SAR ADCs;IEEE Transactions on Circuits and Systems I: Regular Papers;2019-12
4. Digital Blind Background Calibration of Imperfections in Time-Interleaved ADCs;IEEE Transactions on Circuits and Systems I: Regular Papers;2017-06
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