A test set embedding approach based on twisted-ring counter with few seeds

Author:

Zhou Bin,Ye Yi-zheng,Li Zhao-lin,Zhang Jian-wei,Wu Xin-chun,Ke Rui

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference21 articles.

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4. On improving test quality of scan-based BIST;Tsai;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2000

5. P.H. Bardell, W.H. McAnney, Self-testing of multichip logic modules, in: Proceedings of the 1982 International Test Conference, 1982, pp. 200–204.

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1. Optimal Selective Count Compatible Runlength Encoding for SOC Test Data Compression;Journal of Electronic Testing;2016-10-26

2. A Novel Test Data Compression Scheme for SoCs Based on Block Merging and Compatibility;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2014

3. Efficient Test Compression Technique for SoC Based on Block Merging and Eight Coding;Journal of Electronic Testing;2013-11-07

4. Test Pattern Generation Based on Multi-TRC Scan Architecture for Reducing Test Cost;Journal of Low Power Electronics;2012-02-01

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