A Novel Test Data Compression Scheme for SoCs Based on Block Merging and Compatibility-Reference-Cited by-同舟云学术

A Novel Test Data Compression Scheme for SoCs Based on Block Merging and Compatibility

Published:2014 Issue:7 Volume:E97.A Page:1452-1460
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

WU Tiebin¹,LIU Hengzhu¹,ZHANG Botao¹

Affiliation:

1. Institute of Micro-electronics and Micro-processors, College of Computer, National University of Defense Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E97.A/7/E97.A_1452/_pdf

Reference30 articles.

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3. [3] P.T. Gonciari, B. Al-Hashimi, and N. Nicolici, “Improving compression ratio, area overhead, and test application time for system-on-a-chip test data compression/decompression,” Proc. Design, Automation and Test in Europe Conference and Exhibition, pp.604-611, 2002.

4. [4] I. Bayraktaroglu and A. Orailoglu, “Decompression hardware determination for test volume and time reduction through unfied test pattern compaction and compression,” Proc. IEEE VLSI Test Symposium, pp.113-118, 2003.

5. [5] M.X. Yi, H.G. Liang, L. Zhang, and W.F. Zhan, “A novel x-ploiting strategy for improving performance of test data compression,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.18, no.2, pp.324-329, 2010.

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