Optimal Selective Count Compatible Runlength Encoding for SOC Test Data Compression-Reference-Cited by-同舟云学术

Optimal Selective Count Compatible Runlength Encoding for SOC Test Data Compression

Published:2016-10-26 Issue:6 Volume:32 Page:735-747
ISSN:0923-8174
Container-title:Journal of Electronic Testing
language:en
Short-container-title:J Electron Test

Author:

Vohra Harpreet^ORCID,Singh Amardeep

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering

Link

http://link.springer.com/content/pdf/10.1007/s10836-016-5617-x.pdf

Reference33 articles.

1. Bayraktaroglu I, Orailoglu A. (2003) Decompression hardware determination for test volume and time reduction through unified test pattern compaction and compression. In: Proceedings IEEE VLSI test symposium (VTS), pp 113–118.

2. Chandra A, Chakrabarty K (2001) System-on-a-chip data compression and decompression architecture based on Golomb codes. IEEE Trans Comput Aided Des Integr Circuits Syst 20(3):355–368

3. Chandra A, Chakrabarty K (2003) Test data compression and test resource partitioning for system-on-a-chip using frequency-directed run-length (FDR) codes. IEEE Trans Commun 52(8):1076–1088

4. Chandra A, Chakrabarty K (2003) A unified approach to reduce SoC test data volume, scan power and testing time. IEEE Trans Comput Aided Des Integr Circuits Syst 22(3):352–363

5. Chang CH, Lee LJ, Tseng WD, Lin RB (2012) 2n pattern run-length for test data compression. IEEE Trans Comput Aided Des Integr Circuits Syst 31(4):644–648

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Test architecture optimization algorithms for coarse-grain partitioned 3D system-on-chip;Computers and Electrical Engineering;2022-07

2. New scan compression approach to reduce the test data volume;IET Computers & Digital Techniques;2021-03-18

3. Test Stimuli Segmentation and Coding Method;Tehnicki vjesnik - Technical Gazette;2018-08