A reconfigurable 4-GS/s power-efficient floating-point FFT processor design and implementation based on single-sided binary-tree decomposition

Author:

Wei XingORCID,Yang Haigang,Li Wei,Huang Zhihong,Yin Tao,Yu Le

Funder

National Natural Science Foundation of China

Major Program of Beijing Science and Technology

Beijing Key Laboratory of Big Data Technology for Food Safety

Beijing Technology and Business University

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference19 articles.

1. A hybrid SDC/SDF architecture for area and power minimization of floating-point FFT computations;Wang;Proc. IEEE Int. Symp. Circ. Syst.,2016

2. Improved architectures for a floating-point fused dot product unit;Sohn,2013

3. Improved architectures for a fused floating-point add-subtract unit;Sohn;IEEE Trans. Circuits Syst. I,2012

4. A 2.4-GS/s FFT processor for OFDM-based WPAN applications;Tang;IEEE Trans. Circuits Syst. II,2010

5. Power and area minimization of reconfigurable FFT processor: a 3GPP-LTE example;Yang;IEEE J. Solid State Circuits,2012

Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design of Dynamic NOC based Multi-core Floating Point processing element FFT for VLSI Architecture;2023 International Conference on Emerging Research in Computational Science (ICERCS);2023-12-07

2. LCBCTA: The Lowest Computation Burden Cooley-Tukey FFT Algorithm;Proceedings of the 2023 7th International Conference on Electronic Information Technology and Computer Engineering;2023-10-20

3. Design of the vector floating-point unit with high area efficiency;Journal of Physics: Conference Series;2023-06-01

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