Power and Area Minimization of Reconfigurable FFT Processors: A 3GPP-LTE Example-Reference-Cited by-同舟云学术

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Power and Area Minimization of Reconfigurable FFT Processors: A 3GPP-LTE Example

Published:2012-03 Issue:3 Volume:47 Page:757-768
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Yang Chia-Hsiang,Yu Tsung-Han,Markovic Dejan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/6155198/06112185.pdf?arnumber=6112185

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3. Serial Butterflies for Non-Power-of-Two FFT Architectures in 5G and Beyond;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-10

4. A Low Power Clock Gated Approximate Pruned and Truncated HDWT for Power-Efficient ECG Signal Processing;2023 International Conference on Distributed Computing and Electrical Circuits and Electronics (ICDCECE);2023-04-29

5. Efficient Implementation of Complex Multipliers on FPGAs Using DSP Slices;Journal of Signal Processing Systems;2023-04

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