Design of the vector floating-point unit with high area efficiency

Abstract

Abstract With the development of the information age, there is an increasing trend towards mixed precision and vector operations in floating point arithmetic. Traditional floating-point arithmetic is usually implemented using multiple modules to ensure the required speed. Still, this approach significantly increases area and reduces area efficiency, resulting in the wastage of hardware resources. This paper focuses on optimizing speed and area to improve the area’s efficiency. The proposed floating-point unit designed can perform half-precision, single-precision, and double-precision floating-point operations. Under the TSMC 7 nm process, its maximum operating frequency is increased by 5%–37%, the area is reduced by 33%–58%, and area efficiency is increased by 63%–144%.