A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications-Reference-Cited by-同舟云学术

A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications

Published:2022-09 Issue: Volume:86 Page:22-29
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Yan Aibin,Qian Kuikui,Song Tai,Huang Zhengfeng,Ni Tianming,Chen Yu,Wen Xiaoqing

Funder

National Natural Science Foundation of China

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference25 articles.

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3. Design of double-upset recoverable and transient-pulse filterable latches for low power and low-orbit aerospace applications;Yan;IEEE Trans. Aero. Electron. Syst.,2020

4. Radiation-hardened 14T SRAM bitcell with speed and power optimized for space application;Peng;IEEE Trans. Very Large Scale Integr. Syst.,2019

5. Information assurance through redundant design: a novel tnu error-resilient latch for harsh radiation environment;Yan;IEEE Trans. Comput.,2020

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