Author:
Aftabjahani Seyed-Abdollah,Milor Linda
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Reference37 articles.
1. PERT as an aid to logic design;Kirkpatrick;IBM J. Res. Dev.,1966
2. Static timing analysis using backward signal propogation;Lee;Proc. Design Automat. Conf.,2004
3. A methodology for worst-case analysis of integrated circuits;Nassif;IEEE Trans. Comput. Aided Des.,1986
4. Statistical timing analysis using bounds and selective enumeration;Agarwal;IEEE Trans. Comput. Aided Des.,2003
5. Defining statistical timing sensitivity for logic circuits with large-scale process and environmental variations;Li;IEEE Trans. Comput. Aided Des.,2008
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1 articles.
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