Author:
Mahmoudi Azad,Torkzadeh Pooya,Dousti Massoud
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Reference33 articles.
1. Design and comparison of three 20-Gb/s backplane transceivers for duobinary, PAM4, and NRZ data;Lee;IEEE J. Solid State Circ.,2008
2. SE3: will ADCs overtake binary frontends in backplane signaling?;Sheikholeslami,2009
3. Design-space exploration of backplane receivers with high-speed ADCs and digital equalization;Chung,2009
4. A 12.5Gb/s serdes in 65 nm CMOS using a baud-rate ADC with digital receiver equalization and clock recovery;Harwood,2007
5. A 500 mW ADC-Based CMOS AFE with digital calibration for 10 gb/s serial links over kr-backplane and multimode fiber;Cao;IEEE J. Solid State Circ.,2010
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