Revisiting 3DIC benefit with multiple tiers

Author:

Chan Wei-Ting Jonas,Kahng Andrew B.,Li Jiajia

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference49 articles.

1. Block-level designs of die-to-wafer bonded 3D ICs and their design quality tradeoffs;Athikulwongse;Proceedings ASP-DAC,2013

2. Interconnects in the third dimension: design challenges for 3D ICs;Bernstein;Proceedings DAC.,2007

3. CELONCEL: effective design technique for 3-D monolithic integration targeting high performance integrated circuits;Bobba;Proceedings ASP-DAC,2011

4. W.-T. J. Chan, Y. Du, A.B. Kahng, S. Nath, K. Samadi, 3DIC Benefit Estimation and Implementation Guidance from 2DIC Implementation, Proceedings DAC, pp. 1–6.

5. Power benefit study of monolithic 3D IC at the 7nm technology node;Chang;Proceedings ISLPED,2015

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Metal Stack and Partitioning Exploration for Monolithic 3D ICs;2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI);2020-07

2. Electroless nickel underlayer deposited between copper filler and silicon substrate: effect of bath pH;Advances in Materials and Processing Technologies;2020-04-23

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