A Sub-1 V nanopower subthreshold current and voltage reference using current subtraction technique and cascoded active load

Author:

Pal Pratosh Kumar,Nagaria R.K.

Funder

ministry Of Electronics And Information Technology

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference31 articles.

1. Design of Analog CMOS Integrated Circuits;Razavi,2001

2. Enhanced gain low-power cmos amplifiers: a novel design approach using bulk-driven load and introduction to gacoba technique;Dubey;J. Circuits Syst. Comput.,2018

3. Voltage comparison based high speed & low power domino circuit for wide fan-in gates;Pal,2016

4. A new leakage-tolerant high speed comparator based domino gate for wide fan-in or logic for low power vlsi circuits;Kumar;Integration,2018

5. Energy efficient design of direct coupled pass transistor based pulse triggered flip-flop;Pal,2015

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