NoC-DPR: A new simulation tool exploiting the Dynamic Partial Reconfiguration (DPR) on Network-on-Chip (NoC) based FPGA-Reference-Cited by-同舟云学术

NoC-DPR: A new simulation tool exploiting the Dynamic Partial Reconfiguration (DPR) on Network-on-Chip (NoC) based FPGA

Published:2018-09 Issue: Volume:63 Page:204-212
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Hassan Amr,Mostafa Hassan,Fahmy Hossam A.H.

Funder

NTRA

ITIDA

Cairo University

Zewail City of Science and Technology

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference19 articles.

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2. Exploiting the dynamic partial reconfiguration on noc-based FPGA;Hassan,2017

3. NoCTweak: a Highly Parameterizable Simulator for Early Exploration of Performance and Energy of Networks On-chip;Tran,2012

4. ReChannel: describing and simulating reconfigurable hardware in SystemC;Raabe,2008

5. Advanced Methodolgy for Designing Reconfigurable SoC and Application-targeted IP-entities in Wireless Communications Webpage;Adriatic Consortium,2002

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