Design alternatives of Network- on-Chip (NoC) Router microarchitecture for future Communication System
Author:
Affiliation:
1. New Horizon College of Engineering,Department of ECE,Bangalore
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9751777/9752467/09752659.pdf?arnumber=9752659
Reference14 articles.
1. A Low Power and Low Area Router With Congestion-Aware Routing Algorithm for Spiking Neural Network Hardware Implementations
2. CURE: A High-Performance, Low-Power, and Reliable Network-on-Chip Design Using Reinforcement Learning
3. Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique
4. Blocking Performance And Analysis Of Routing And Wavelength Assignement Using Shortest Path Routing Algorithm In All-Optical Network
5. Quality of service (QoS) and priority aware models for energy efficient and demand routing procedure in mobile ad hoc networks
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1. Enhancing High-Speed Data Communications: Optimization of Route Controlling Network on Chip Implementation;IEEE Access;2024
2. Wave-Pipelined Source-Synchronous Circuit-Switched Data Transmission;2023 12th International Conference on Modern Circuits and Systems Technologies (MOCAST);2023-06-28
3. Parametric Investigation of Antenna designs for 5G Communications;2023 International Conference on Recent Trends in Electronics and Communication (ICRTEC);2023-02-10
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