Author:
Saha Rajesh,Pundir Yogendra Pratap,Kumar Pal Pankaj
Funder
Ministry of Electronics and Information technology
National Institute of Technology, Raipur
Ministry of Education, India
Subject
Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Reference32 articles.
1. International Roadmaps for Devices and System (IRDS), 2020. [Online]. Available: https://irds.ieee.org/editions/2020.
2. M. Chang, P. Rosenfeld, S. Lu and B. Jacob, “Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM,” in: Proc. 19th International Symposium on High Performance Computer Architecture (HPCA)-IEEE, Shenzhen, China, 2013, pp. 143-154, doi: 10.1109/HPCA.2013.6522314.
3. Memory leads the way to better computing;Wong;Nat. Nanotechnol.,2015
4. Efficient Cache Resizing policy for DRAM-based LLCs in ChipMultiprocessors;Agarwalla;J. Syst. Architect.,2021
5. Differential Spin Hall Effect-Based Nonvolatile Static Random-Access Memory for Energy-Efficient and Fast Data Restoration Application;Shreya;IEEE Trans. Magn.,2019
Cited by
23 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献