Thin Si wafer substrate bonding and de-bonding below 250 °C for the monolithic 3D integration-Reference-Cited by-同舟云学术

Thin Si wafer substrate bonding and de-bonding below 250 °C for the monolithic 3D integration

Published:2018-10 Issue: Volume:281 Page:222-228
ISSN:0924-4247
Container-title:Sensors and Actuators A: Physical
language:en
Short-container-title:Sensors and Actuators A: Physical

Author:

Jeon Yu-Rim,Han Hoonhee,Choi Changhwan

Funder

Nano Material Technology Development Program

National Research Foundation of Korea

Ministry of science, ICT & Future Planning

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Metals and Alloys,Surfaces, Coatings and Films,Condensed Matter Physics,Instrumentation,Electronic, Optical and Magnetic Materials

Reference24 articles.

1. Effect of Ultrasound on Copper Filling of High Aspect Ratio Through-Silicon Via (TSV)

2. Through silicon via: From the CMOS imager sensor wafer level package to the 3D integration

3. R&D Overview of 3D Integration Technology Using TSV Worldwide and in Japan

4. 3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

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