A Low Power Reconfigurable Encoder for Flash ADCs-Reference-Cited by-同舟云学术

A Low Power Reconfigurable Encoder for Flash ADCs

Published:2016 Issue: Volume:25 Page:574-581
ISSN:2212-0173
Container-title:Procedia Technology
language:en
Short-container-title:Procedia Technology

Author:

Varghese George Tom,Mahapatra Kamalakanta

Publisher

Elsevier BV

Subject

General Earth and Planetary Sciences,General Environmental Science

Reference8 articles.

1. Fat-tree encoder design for ultrahigh speed flash analog to digital converters;Lee;I proc IEEE Mid-west Symp. Circuits Syst,2002

2. An Encoder for a 5GS/s 4bit flash A/D converter in 0.18um CMOS;Sheikhaei;Canadian Conference on Electrical and Computer Engineering,2005

3. Jan M Rabaey, Anantha Chandrakasan, Borivoje Nikolic, “Digital Integrated Circuits, a design perspective”, second edition, Prentice Hall 2011.

4. Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs;Vudadha;25 th IEEE International conference on VLSI Design,2012

5. A study of digital decoders in flash analog-to-digital converters;Sall Erik;Proc. of International symposium on Circuits and systems,2004

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1. Design of a Novel Encoder for Flash Analog to Digital Converter;2022 IEEE International Conference on Data Science and Information System (ICDSIS);2022-07-29

2. A 0.48 mW High Performance 4-Bit Flash ADC for System-on-Chip Applications in 90 nm CMOS Technology;Lecture Notes in Electrical Engineering;2020-09-20

3. Methodology and comparative design of an efficient 4‐bit encoder with bubble error corrector for 1‐GSPS flash type ADC;IET Circuits, Devices & Systems;2020-07-15

4. Approach for low power high speed 4‐bit flash analogue to digital converter;IET Circuits, Devices & Systems;2020-06-15

5. Resolution Selective 2–6-Bit Flash ADC in 45 nm Technology;Lecture Notes in Electrical Engineering;2020