Author:
Smith S.C.,DeMara R.F.,Yuan J.S.,Hagedorn M.,Ferguson D.
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Reference20 articles.
1. K.M. Fant, S.A. Brandt, NULL convention logic: a complete and consistent logic for asynchronous digital circuit synthesis, International Conference on Application Specific System, Architectures, and Processors 1996, pp. 261–273.
2. Theseus Logic, Inc. Press Release, Motorola and Theseus Logic to Jointly Develop Clockless ICs. www.theseus. com/FramesPress. htm: 1999.
3. C. Wang, D. Parker, R. Jorgenson, K. Fant, Technology Independent Design Using NULL Convention Logic, www.theseus.com/TechInd/index.html: 1998.
4. I.E. Sutherland, Micropipelines, Communications of the ACM, New york 32 (6) (1989) 720–738.
5. P. Day, J. Viv. Woods, Investigation into micropipeline latch design styles, IEEE Trans. VLSI Systems 3 (2) (1995) 264-272.
Cited by
29 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Error Resilient Sleep Convention Logic Asynchronous Circuit Design;2023 21st IEEE Interregional NEWCAS Conference (NEWCAS);2023-06-26
2. Power Consumption Improvements in AES Decryption Based on Null Convention Logic;International Journal of Circuits, Systems and Signal Processing;2021-04-07
3. Further Speedup of a Large Word-Width High-Speed Asynchronous Multiply and Accumulate Unit;2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS);2020-08
4. Formal Verification of Completion-Completeness for NCL Circuits;2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS);2020-08
5. Automated verification of input completeness for NCL circuits;Electronics Letters;2018-10