Investigation into micropipeline latch design styles
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Link
http://xplorestaging.ieee.org/ielx4/92/8756/00386226.pdf?arnumber=386226
Cited by 30 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Investigation of asynchronous pipeline circuits based on bundled-data encoding: Implementation styles, behavioral modeling, and timing analysis;Tsinghua Science and Technology;2022-06
2. Relative Timing Latch Controller with Significant Improvement on Power, Performance, and Robustness;2021 6th International Conference on Integrated Circuits and Microsystems (ICICM);2021-10-22
3. Comparison of Pipelined Asynchronous Circuits Designed for FPGA;Proceedings of the 3rd International Conference on Applications in Information Technology;2018-11
4. The Design of High-Performance Dynamic Asynchronous Pipelines: High-Capacity Style;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2007-11
5. The Design of High-Performance Dynamic Asynchronous Pipelines: Lookahead Style;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2007-11
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