Modeling and estimation of process-induced stress in the nanowire field-effect-transistors (NW-FETs) on Insulator-on-Silicon substrates with high-k gate-dielectrics-Reference-Cited by-同舟云学术

Modeling and estimation of process-induced stress in the nanowire field-effect-transistors (NW-FETs) on Insulator-on-Silicon substrates with high-k gate-dielectrics

Published:2016-10 Issue: Volume:98 Page:194-202
ISSN:0749-6036
Container-title:Superlattices and Microstructures
language:en
Short-container-title:Superlattices and Microstructures

Author:

Chatterjee Sulagna^ORCID,Chattopadhyay Sanatan

Funder

Council of Scientific and Industrial Research, India

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,General Materials Science

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5. Strain-dependent characteristics of triangular silicon nanowire-based field-effect transistors on flexible plastics;Koo;Jpn. J. Appl. Phys.,2011

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