CMOS technologies in the 100nm range for rad-hard front-end electronics in future collider experiments
Author:
Publisher
Elsevier BV
Subject
Instrumentation,Nuclear and High Energy Physics
Reference8 articles.
1. Challenges and benefits of designing readout ASICs in advanced technologies
2. Radiation-induced edge effects in deep submicron CMOS transistors
3. Total ionizing dose effects on the noise performances of a 0.13 /spl mu/m CMOS technology
4. Layout techniques to enhance the radiation tolerance of standard CMOS technologies demonstrated on a pixel detector readout chip
5. MOSFET optimization in deep submicron technology for charge amplifiers
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1. A 78.5-dB SNDR Radiation- and Metastability-Tolerant Two-Step Split SAR ADC Operating Up to 75 MS/s With 24.9-mW Power Consumption in 65-nm CMOS;IEEE Journal of Solid-State Circuits;2019-02
2. Quadruple Well CMOS MAPS With Time-Invariant Processor Exposed to Ionizing Radiation and Neutrons;IEEE Transactions on Nuclear Science;2014-08
3. A fast and low noise charge sensitive preamplifier in 90 nm CMOS technology;Journal of Instrumentation;2012-01-03
4. Total ionizing dose effects in elementary devices for 180-nm flash technologies;Microelectronics Reliability;2011-08
5. A Prototype Pixel Readout IC for High Count Rate X-Ray Imaging Systems in 90 nm CMOS Technology;IEEE Transactions on Nuclear Science;2010-06
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