Design and analysis of an efficient low power low delay low leakage clock keeper domino logic-Reference-Cited by-同舟云学术

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Design and analysis of an efficient low power low delay low leakage clock keeper domino logic

Published:2024-06 Issue: Volume:8 Page:100525
ISSN:2772-6711
Container-title:e-Prime - Advances in Electrical Engineering, Electronics and Energy
language:en
Short-container-title:e-Prime - Advances in Electrical Engineering, Electronics and Energy

Author:

N Kurumaiah,Joseph M. Kezia,Sekhar P. Chandra

Publisher

Elsevier BV

Reference20 articles.

1. Dynamic noise analysis with capacitive and inductive coupling;Choi,2002

2. Analysis and design of lector-based dual-Vt domino logic with reduced leakage current;Gupta;Circuit World,2017

3. Noise-tolerant dynamic CMOS circuits design by using true single-phase clock latching technique;Wey;Int. J. Circuit Theor. Appl.,2015

4. Robust low leakage controlled keeper by current-comparison domino for wide fan-in gates;Peiravi;Integration,2012

5. Impact of technology scaling on the performance of domino CMOS logic;Sharroush,2008

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