Improvement of gate CD imbalance for a 0.35μm logic technology
Author:
Publisher
Elsevier BV
Subject
Mechanical Engineering,Mechanics of Materials,Condensed Matter Physics,General Materials Science
Reference11 articles.
1. Mechanism for anisotropic etching of phoresist-masked polycrystalline silicon in HBr plasmas;Cheng;J Vac Sci Technol B,1996
2. Orshansky M, Milor L, Nguyen L, Hill G, Peng Y, Hu C. Intra-field gate CD variability and its impact on circuit performance. IEDM Tech Dig 1999; 479.
3. Simulating the impact of pattern-dependent poly CD variation on circuit performance;Stine;IEEE Trans Semicond Manuf,1998
4. Study of the impact of the time-delay effect on the critical dimension of a tungsten silicide/polysilicon gate after reactive ion etching;Lin;J Vac Sci Technol A,2000
5. Thakar G, McNeil V, Madan S, Riemenschneider B, Rogers D, McKee J, Eklund R, Chapman R. A manufacturable high performance quarter micron CMOS technology using I-line lithography and gate linewidth reduction etch process. Proceeding of the Symposium on VLSI Technology, 1996. p. 216.
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