A methodology for algorithm regularization and mapping into time-optimal VLSI arrays-Reference-Cited by-同舟云学术

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A methodology for algorithm regularization and mapping into time-optimal VLSI arrays

Published:1993-01 Issue:1 Volume:19 Page:33-61
ISSN:0167-8191
Container-title:Parallel Computing
language:en
Short-container-title:Parallel Computing

Author:

Barada H,El-Amawy A

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Graphics and Computer-Aided Design,Computer Networks and Communications,Hardware and Architecture,Theoretical Computer Science,Software

Reference25 articles.

1. Why systolic architectures?;Kung;Comput.,1982

2. Systematic approaches to the design of algorithmically specified systolic arrays;Fortes,1985

3. VLSI Array Processors;Kung,1988

4. Regular iterative algorithms and their implementation on processor arrays;Rao,1985

5. An algebra for VLSI algorithm design;Kung,1983

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Complexity of matrix product on modular linear systolic arrays for algorithms with affine schedules;Journal of Parallel and Distributed Computing;2006-03

2. Matrix-vector multiplication on a fixed-size linear systolic array;Computers & Mathematics with Applications;2000-11

3. Data reordering converter: an interface block in a linear chain of processing arrays;Microelectronics Journal;2000-01

4. The design of optimal planar systolic arrays for matrix multiplication;Computers & Mathematics with Applications;1997-03

5. Designing of processor-time optimal systolic arrays for band matrix-vector multiplication;Computers & Mathematics with Applications;1996-07

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