Author:
Chiang Tsung-Hsi,Dung Lan-Rong
Subject
Hardware and Architecture,Information Systems,Software
Reference28 articles.
1. Ashar, P., Bhattacharya, S., Raghunathan, A., Mukaiyama, A., 1998. Verification of rtl generated from scheduled behavior in a high-level synthesis flow. In: Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, pp. 517–524.
2. Design of VHDL-based totally self-checking finite-state machine and data-path descriptions;Bolchini;IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2000
3. A compositional model for the functional verification of high-level synthesis results;Borrione;IEEE Transactions on VLSI Systems,2000
4. Efficient implementation of a BDD package;Brace;ACM/IEEE Design Automation Conference,1990
5. Symbolic Boolean manipulation with ordered binary-decision diagrams;Bryant;ACM Computing Surveys,1992
Cited by
3 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Implementing an Efficient Path Based Equivalence Checker for Parallel Programs;Proceedings of the ACM Workshop on Software Engineering Methods for Parallel and High Performance Applications;2016-05-31
2. Formal verification of code motion techniques using data-flow-driven equivalence checking;ACM Transactions on Design Automation of Electronic Systems;2012-06
3. Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital Circuits;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2010-03