Bandgap engineering in vertical P-MOSFETs

Author:

Chen Xiangdong,Liu Kou-chen,Ray Samit,Banerjee Sanjay

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference11 articles.

1. CMOS scaling into the nanometer regime;Taur;Proc IEEE,1997

2. Effect of the Ge mole fraction on the subthreshold slope and leakage current of the vertical Si/Si1−xGex MOSFETs;Collaert;Solid-State Electron,1999

3. New structural approach for reducing punchthrough current in deep deep submicrometer MOSFETs and extending MOSFET scaling;Hareland;IEEE Electron Lett,1993

4. Chen X, Ouyang Q, Onsongo DM, Jayanarayanan SK, Tasch A, Banerjee SK. Vertical P-MOSFETs with heterojunction between source/drain and channel. Proceedings of the IEEE Device Research Conference, Denver; 2000. p. 25–8

5. Tasch A. The challenges in achieving sub-100 nm MOSFETs. Second Annual IEEE International Conference on Innovative Systems in Silicon. Proceedings, 1997. p. 52–60

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1. Industry Examples at the State-of-the-Art;Silicon Heterostructure Devices;2007-12-13

2. High-k gate oxide for silicon heterostructure MOSFET devices;Journal of Materials Science: Materials in Electronics;2006-09

3. Industry Examples at the State-of-the-Art;Silicon Heterostructure Handbook;2005-11

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