A low-leakage VLSI CMOS/SOS process with thin epi layers
Author:
Publisher
Elsevier BV
Subject
General Engineering
Reference2 articles.
1. Improvement of SOS Device Performance by Solid-Phase Epitaxy;Yohii,1981
2. Feasibility study of SOS VLSI: Capacitance Analysis in Downward Scaling and Improvement of Thin-Films by Solid-Phase Epitaxy;S,1981
Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. The effect of post-implantation annealing temperature on the deep states present in SIMOX MOSFET’s as observed using enhancement mode current DLTS;Journal of Electronic Materials;1990-05
2. Multiple-threshold-voltage CMOS/SOS by focused ion beams;Solid-State Electronics;1988-02
3. MOSFET performance enhancement by improved SOS material processes;Microelectronics Journal;1984-09
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