Partial error tolerance for bit-plane FIR filter architecture-Reference-Cited by-同舟云学术

Partial error tolerance for bit-plane FIR filter architecture

Published:2009-05 Issue:5 Volume:63 Page:398-405
ISSN:1434-8411
Container-title:AEU - International Journal of Electronics and Communications
language:en
Short-container-title:AEU - International Journal of Electronics and Communications

Author:

Ćirić Vladimir,Kolokotronis Jelena,Milentijević Ivan

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering

Reference12 articles.

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3. Hsieh T-Y, Lee K-J, Breuer M. Reduction of detected acceptable faults for yield improvement via error-tolerance. In: Proceedings of the conference on design, automation and test in Europe, Nice, France, 2007. p. 1599–1604.

4. Fault tolerance: the electrical engineering handbook;Johnson,1993

5. International Technology Roadmap for Semiconductors: Recommendations. 〈http://public.itrs.net/〉, 2001.

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