A power scalable 2–10 Gb/s PI-based clock data recovery for multilane applications

Author:

Lv Fangxu,Zheng Xuqiang,Zhao Feng,Wang Jianye,Yue Shigang,Ziqiang Wang ,Cao Weidong,He Yajun,Zhang Chun,Jiang Hanjun,Wang Zhihua

Funder

China National Science Technology Major Project

STEP2DYNA

Publisher

Elsevier BV

Subject

General Engineering

Reference21 articles.

1. A multichannel serial link receiver with dual-loop clock-and-data recovery and channel equalization;Kalantari;IEEE Trans. Circuits Syst. I Reg. Pap.,2013

2. Clocking analysis, implementation and measurement techniques for high-speed data links − A tutorial;Casper;IEEE Trans. Circuits Syst. I Reg. Pap.,2009

3. A 6.5 Mb/s to 11.3 Gb/s continuous-rate clock and data recovery;Kenney,2014

4. A power-scalable 7-Tap FIR equalizer with tunable active delay line for 10-to-25Gb/s multi-mode fiber EDC in 28nm LP-CMOS;Mammei,2014

5. A 2.6mW 370MHz-to-2.5GHz open-loop quadrature clock generator;Kim,2008

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