Author:
Biswal Pradeep Kumar,Biswas Santosh
Reference40 articles.
1. Compaction-based concurrent error detection for digital circuits;Almukhaizim;Microelectron. J.,2005
2. A theory of timed automata;Alur;Theor. Comput. Sci.,1994
3. A novel low power pattern generation technique for concurrent BIST architecture;Balasubrahamanyam;Int. J. Comput. Technol. Appl.,2012
4. A formal approach to on-line monitoring of digital VLSI circuits;Biswas;J. Electron. Test.,2005
5. S. Biswas, S. Mukhopadhyay, A. Patra, D. Sarkar, Concurrent testing of digital circuits for advanced fault models, in: DDECS, 2006, pp. 202–207.
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