1. The iSLIP scheduling algorithm for input-queued switches;McKeown;IEEE/ACM Trans. Netw.,1999
2. Designing and implementing a fast crossbar scheduler;Gupta;IEEE Micro,1999
3. Y. Li, S. Panwar, H.J. Chao, On the performance of a dual round-robin switch, in: Proceedings of the IEEE Twentieth Annual Joint Conference of the IEEE Computer and Communications Societies, (INFOCOM), vol. 3, 2001 pp. 1688–1697.
4. M.J. Adiletta, W. Wheeler, J. Redfield, D. Cutter, G. Wolrich, SRAM controller for parallel processor architecture including address and command queue and arbiter, US Patent 6,427,196, 2002.
5. J. Reed, N. Manjikian, A dual round-robin arbiter for split-transaction buses in system-on-chip implementations, in: Canadian Conference on Electrical and Computer Engineering, vol. 2, IEEE, 2004, pp. 835–840.