Substrate BOX engineering to mitigate the self-heating induced degradation in nanosheet transistor

Author:

Rathore Sunil,Jaisawal Rajeewa Kumar,Gandhi Navneet,Kondekar P.N.,Bagga NavjeetORCID

Publisher

Elsevier BV

Subject

General Engineering

Reference38 articles.

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4. Sresta Valasa1, Shubham Tayal, and Laxman Raju Thoutam, “Design insights into thermal performance of vertically stacked JL-NSFET with high-k gate dielectric for sub 5-nm technology node,” ECS J. Solid State ss8777/ac6627.

5. Circuit analysis and optimization of GAA nanowire FET towards low power and high switching;Sreenivasulu;Silicon,2022

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